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Anyone who has ever built anything knows the importance of precision every step of the way. Build a brick wall? You better check every row to make sure you’re staying level and square, or you might find that wall crumbles in just a few months. To build a home? If you don’t leave enough room in the walls for pipes, wires, and insulation, you won’t be very happy living there.
The same principle applies to integrated circuit (IC) design. That’s the whole point of having process design kits (PDKs), rulesets, and verification tools. They help all designers ensure that the design they create is properly constructed and complies with all “building codes” that guarantee manufacturability and performance.
For years, however, designers have used a few shortcuts here and there. When implementing digital design, it’s not always practical to stream your design database, run a full batch design rules check (DRC) flow, and then debug errors. . Running a batch DRC iteration takes time. You need to merge your P&R data with IP data to generate a full GDSII/OASIS database, then run full batch DRC (usually an overnight process), then triage and debug errors. And you’re going to have millions of errors in the early stages of implementation, just because your design is far from complete. Once you find and fix the errors, you have to repeat the whole process (and again and again).
As a workaround, companies that create placement and routing (P&R) tools provide a limited subset of rule checks that designers can use to quickly check layouts for DRC errors, implement fixes and verify the fix. This approach works great for gross layout errors and saves designers a lot of time. However, these built-in P&R verifiers do not and cannot implement DRC at the approval level. The purpose of their existence is to perform simple and basic checks. At some point, designers must find and fix these complex, “last mile” DRC errors using batch DRC and manual debugging and layout adjustments. And we’re not talking about a handful of errors, they can often range from a few hundred to a few thousand, especially for today’s large, complex designs.
So, you want to improve and speed up your design implementation flow, but you still need to make sure that you’re building that design correctly at every step. How are you doing that? One solution is to add real-time approval quality DRC to your P&R environment. Electronic Design Automation (EDA) companies have introduced new tools and features that allow designers to access approval rule sets and DRC engines from within their P&R environment.
One of the companies that made this possible is Siemens EDA, part of Siemens Digital Industries Software. Their Caliber RealTime Digital interface makes Caliber nmDRC trust verification available from within the P&R tool. Using the same Caliber nmDRC platform and approval engine used in batch DRC streams, engineers can perform multiple check/fix/verify iterations without needing to stream databases and run a batch DRC verification (Figure 1). Caliber RealTime Digital provides direct calls to Caliber analysis engines running foundry-qualified approval Caliber rulesets. Caliber RealTime Digital can perform all verification that can be performed with the Caliber nmDRC platform, including recommended rules, pattern matching, equation-based DRC, preferred metal direction rules, and multiple patterns. Caliber engines perform rapid, incremental verification near shapes being edited, providing near-instantaneous feedback on design rule violations and potential sensitivity to systematic variation (measured by compliance with recommended rules).
Figure 1. With On-Demand Approval Quality DRC in the P&R environment, engineers can perform multiple rapid iterations of DRC remediation and verification.
Designers can also use this immediate approval DRC feedback to perform what-if analyzes on design rule violations and recommended rule compliance in P&R tools (Figure 2). Not only does this capability allow designers to devote even more dedicated verification time and effort to achieving power, performance, and area (PPA) goals, but it also provides a quick way for designers working in a new process node to experiment with a new rule. checks. Companies that can successfully design a new process node can get to market faster, gain a competitive advantage, and reap the benefits that come with being first.
Figure 2. With access to a full range of physical verification features, engineers can solve complex layout problems quickly.
With on-demand access to approval-grade DRC from their P&R tool, digital designers can produce a DRC-specific design that is resistant to manufacturing variability issues and optimized for the most desirable performance and operational characteristics. , while still adhering to tighter withdrawal schedules. In rapidly changing markets, tools like Caliber RealTime Digital provide operational advantages while ensuring that design companies can consistently deliver high-quality products.
Srinivas Velivala is Senior Product Manager at Caliber Design Solutions at Siemens EDA, part of Siemens Digital Industries Software. Its main objective is the development of Caliber integration and interface tools and technologies. Prior to joining Siemens EDA, he designed high-density SRAM compilers. Along with over 12 years of product design and management experience, Srinivas holds a BS and MS in Electrical and Computer Engineering. He can be contacted at [email protected]