SAN JOSE, Calif., July 22, 2021 – Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the delivery of Cadence Cerebrus Intelligent Chip Explorer, a new machine learning (ML)-based tool that automates and makes evolve the digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity up to 10x compared to a manual approach while achieving up to 20% power, performance and area (APP).
With the addition of Cerebrus to the broader digital product portfolio, Cadence offers an advanced digital ML-enabled complete workflow from synthesis to implementation and approval. The new tool is cloud-enabled and uses highly scalable compute resources from leading cloud providers to quickly meet design requirements across a wide range of markets, including consumer, large-scale computing, 5G communications, automotive and mobile. For more information about Cerebrus, please visit www.cadence.com/go/cerebruspr.
Cerebrus offers its customers the following advantages:
- ML Reinforcement: Quickly find flow solutions that human engineers couldn’t naturally try or explore, improving PPA and productivity.
- ML Model Reuse: Automatically apply design learnings to future designs, reducing time to better results.
- Improved Productivity: Allows a single engineer to automatically optimize the RTL-to-full GDS stream for many blocks simultaneously, allowing entire design teams to be more productive.
- Massively Distributed Computing: Provides scalable on-premises or cloud-based design exploration for faster workflow optimization.
- Easy-to-use interface: The powerful user cockpit enables interactive analysis of results and management of runs to gain valuable insight into design metrics.
“Previously, design teams lacked an automated way to reuse historical design knowledge, leading to excessive time spent on manual relearning with each new project and lost margins,” said Dr Chin- Chi Teng, Senior Vice President and General Manager. manager within the Digital & Signoff group at Cadence. “The delivery of Cerebrus marks a revolution in the EDA industry with ML-driven digital chip design where engineering teams have a greater opportunity to have a higher impact in their organizations as they can offload processes manuals. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus enables designers to achieve PPA goals much more efficiently.
Cerebrus is part of Cadence’s larger digital complete workflow, working seamlessly with Genus Synthesis Solution, Innovus Implementation System, Tempus Timing Approval Solution, Joules RTL Power Solution, Voltus IC Power Integrity and the Pegasus Verification System to provide customers with a fast path to design closure and better predictability. The new tool and broader flow support the company’s Intelligent System Design strategy, which enables pervasive intelligence for design excellence.
Cadence is an established leader in electronics design, backed by more than 30 years of expertise in calculation software. The company applies its underlying Intelligent Systems Design strategy to deliver software, hardware and intellectual property that turn design concepts into reality. Cadence’s customers are the most innovative companies in the world, delivering extraordinary electronic products ranging from chips to boards to systems for the most dynamic applications in the market, including consumer computing, large-scale computing , 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven consecutive years, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.