Cadence Expands Digital Design Leadership with Revolutionary ML-Based Cerebrus, Delivering Unparalleled Productivity and Quality of Results


SAN JOSE, Calif.–(BUSINESS WIRE)–Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced delivery of the Cadence® Cerebrus™ Intelligent Chip Explorer, a new machine learning (ML) based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals. The combination of Cerebrus and the Cadence RTL-to-signoff flow offers advanced chip designers, CAD teams and IP developers the ability to improve engineering productivity up to 10x compared to a manual approach while achieving up to 20% power, performance and area (APP).

With the addition of Cerebrus to the broader digital product portfolio, Cadence offers the industry’s most advanced ML-enabled complete digital workflow, from synthesis to implementation and approval. The new tool is cloud-enabled and uses highly scalable compute resources from leading cloud providers to quickly meet design requirements across a wide range of markets, including consumer computing, large-scale computing, 5G communications, automotive and mobile telephony. For more information about Cerebrus, please visit

Cerebrus offers its customers the following advantages:

  • ML frame: Quickly find flow solutions that human engineers couldn’t naturally try or explore, improving PPA and productivity.
  • Reusing the ML model: Allows design learnings to be automatically applied to future designs, reducing the time it takes to achieve better results.
  • Improved productivity: Enables a single engineer to automatically optimize the full RTL to GDS stream for many blocks simultaneously, allowing full design teams to be more productive.
  • Massively distributed computing: Provides scalable on-premises or cloud-based design exploration for faster workflow optimization.
  • Easy to use interface: A powerful user cockpit enables interactive analysis of results and management of runs to gain valuable insight into design metrics.

“Previously, design teams lacked an automated way to reuse historical design knowledge, leading to excessive time spent on manual relearning with each new project and lost margins,” said Dr Chin- Chi Teng, Senior Vice President and General Manager. manager within the Digital & Signoff group at Cadence. “The delivery of Cerebrus marks a revolution in the EDA industry with ML-driven digital chip design where engineering teams have a greater opportunity to have a higher impact in their organizations as they can offload processes manuals. As the industry continues to move toward advanced nodes and design size and complexity increase, Cerebrus enables designers to achieve PPA goals much more efficiently.

Cerebrus is part of the complete Cadence digital workflow, working seamlessly with Genus™ Synthesis Solution, Innovus™ Implementation System, Tempus™ Timing Approval Solution, Joules™ RTL Power Solution, Voltus™ IC Power Integrity solution and the Pegasus™ verification system to provide customers with a fast path to design closure and improved predictability. The new tool and broader flow support the company’s Intelligent System Design™ strategy, which enables pervasive intelligence for design excellence.

Customer Approvals

“To effectively optimize the performance of new products that use emerging process nodes, the digital implementation flows used by our engineering team must be continually updated. Automated design flow optimization is key to achieving product development at a much higher throughput. Cerebrus, with its innovative ML capabilities, and Cadence RTL-to-signoff tools provided automated flow optimization and floor plan exploration, improving design performance by more than 10%. Following this success, the new approach will be adopted in the development of our latest design projects.

– Satoshi Shibatani, Director, Department of Digital Design Technologies, Shared EDA R&D Division, Renesas

“As Samsung Foundry continues to deploy up-to-date process nodes, the effectiveness of our Design Technology Co-Optimization (DTCO) program is very important, and we are always looking for innovative ways to exceed PPA in the implementation of chips. As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and Cadence’s digital implementation flow on several apps. We’ve seen over 8% power reduction on some of our most critical blocks in just days, versus months of manual effort. Additionally, we use Cerebrus for automated sizing of the floor plan electrical distribution network, which has improved final design time by more than 50%. With Cerebrus and the digital implementation flow delivering better PPA and significant productivity improvements, the solution has become a valuable addition to our DTCO program.

– Sangyun Kim, Vice President, Design Technology, Samsung Foundry

About cadence

Cadence is an established leader in electronics design, backed by more than 30 years of expertise in calculation software. The company applies its underlying intelligent systems design strategy to deliver software, hardware and intellectual property that turn design concepts into reality. Cadence’s customers are the most innovative companies in the world, delivering extraordinary electronic products ranging from chips to boards to systems for the most dynamic applications in the market, including consumer computing, large-scale computing , 5G communications, automotive, mobile, aerospace, industrial and healthcare. For seven consecutive years, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at

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